1. Field of the Invention
The present invention relates to a packaging technique, and in particular, relates to a packaging technique of a capacitive coupler structure.
2. Description of the Related Art
A capacitive coupler is often used for isolation. The capacitive coupler can perform signal exchanges without current passing therethrough, and noise and damage resulting from ground potential difference can thus be avoided.
A conventional capacitive coupler has a poor performance due to a high RC delay because both of a receiver and a transmitter are electrically connected to the capacitor via wire bonding.
A system on chip (SOC) capacitive coupler may provide a fast data transforming rate, low power consumption and high electromagnetic susceptibility. In the SOC capacitive coupler, the capacitor and the receiver are disposed on a same substrate for reducing a resistance between the capacitor and the receiver. Referring to FIG. 1, a capacitor 120 is directly disposed on a receiver chip 130, and the capacitor 120 is electrically connected to a transmitter chip 140 via wire bonding 190.
However, in order to have a high breakdown voltage (e.g., >5 kV), the SOC capacitive coupler needs to use a thick capacitor dielectric layer, for example, about 1.2 μm. Therefore, a problem of wafer warpage may arise. US Pub. 2008/0277761 discloses an SOC capacitive coupler comprising a capacitor using stacked layers formed of multiple dielectric materials for reducing the thickness of the capacitor insulating layer. However, it may increase production cost of the SOC capacitive coupler.
Thus, development of a capacitive coupler which has a low RC delay and low production cost is needed.